Arm launches Neoverse CSS N4 for 3nm CPUs, DPUs with PCIe Gen7

Arm has launched the Neoverse CSS N4 compute subsystem, IP designed to let companies quickly build next-generation power-efficient CPUs and DPUs. The new subsystem is built for 3nm process technology and supports 8 to 128 cores per die, with the Neoverse N4 cores making Armv9.3 architecture the baseline for the design. The cores are tuned to run at up to 3.8GHz given their focus on power-efficient compute, and they add support for FP8 and MMLA instructions.

The launch matters because Neoverse CSS has appeared in more products over the past few years, making this an important release for the industry. Arm positions the CSS line as a way for chipmakers to assemble a full subsystem rather than design every block from scratch. The N4 package ties together the CPU cores, memory, I/O, and die-to-die interfaces through the Arm Neoverse CMN S4 Interconnect, the fabric at the center of the subsystem. CMN S4 supports up to a 16x16 mesh interconnect and fully coherent multi-chiplet connectivity using the CHI C2C protocol.

On the memory side, the new generation brings support for LPDDR6 as well as DDR5 and MRDIMMs at 8000-12000MT/s speeds. For I/O, the CSS N4 offers up to 128 lanes of PCIe Gen7, a signal that the design targets CPUs coming out at least one generation from now rather than systems shipping in the current cycle.

ServeTheHome notes that one of the neatest N-series CSS implementations seen recently is the XSight Labs E1, a 64-core Arm 800G DPU built on the earlier Neoverse CSS N2 design with 64 Arm Neoverse N2 cores. For a startup like XSight Labs, using a Neoverse CSS design makes sense because Arm does much of the heavy integration work, letting a smaller company bring a high-end DPU to market without building the full subsystem in-house.

The N4 announcement extends a pattern in which Arm has steadily pushed its CSS offerings into more products across the server market. The new subsystem's PCIe Gen7 support and 3nm process target suggest the first N4-based silicon will arrive in a later hardware generation, with the design aimed at the power-efficient end of the compute spectrum rather than raw top-end clock speeds.

Arm has not detailed which customers have committed to building N4-based parts, and no shipping products based on the CSS N4 have been announced. The company has not disclosed pricing or a timeline for when the first N4 designs will tape out or reach the market. What is clear is that the subsystem is meant to serve both CPU and DPU builders, giving Arm a single platform for the two fastest-growing categories of data center silicon.